Satellite TMTC interface
A large satellite company based in the UK required a simulator for the communication and control interfaces of a satellite payload. These simulators are used during the payload assembly, integration and test phases of the satellite build, to provide various command and telemetry protocols to control and read back the payload status before it is integrated with the flight space-craft bus. Traditionally these simulators have been custom built hardware platforms with a propriety software interface built by in house engineering teams.
To reduce development costs and timescales, Vadis designed this system with the majority of the equipment based around COTS equipment in the form of a National Instruments PXI chassis and various standard NI digital, analogue, switch and reconfigurable IO (FPGA) cards to provide the necessary functionality. Since the actual payload configuration was not stable at the outset of the project, the interface unit in the form of a specially designed 3U 19-inch rack mounted box was conceived with the standard NI outputs wired into breakout boards which allowed for an element of flexibility with the internal wiring. The output of the interface unit feeds many custom harnesses to the payload.
- 128 high voltage (20V & 30V) pulsed command signals with programmable pulse widths.
- 2 PXI-6512 64 channel digital output cards
- VCC sourced from PSUs built in to the in-terface unit
- Pulsed signal at the correct voltage and variable width using LabVIEW and DAQmx functions.
- User customisation of the control labels on the GUI, DAQ device, port & channel plus the pulse width by editing a simple ASCII file.
- 40 switch controlled voltage inputs
- PXI-2570 40 SPDT switch card
- VCC sourced from PSU built in to the inter-face unit
- Switch control LabVIEW software to make/break the voltage control signal
- 4 custom FPGA defined differential LSSB trans-mit and receive communications
- PXI-7851R Reconfigurable mixed IO (FPGA) card
- Low speed serial bus provided to the satel-lite in short 2byte bursts
- Specific FPGA code to provide the re-quired timing for the clock, valid and data lines
- Custom RS485 line driver interface board to meet physical communication interface
- Windows software to read/write to FPGA
- 4 custom LVDS communication channels
- PXI-6561 100MHz LVDS card
- LabVIEW transmit and receive code written using standard High-Speed Digital Input Output (HSDIO) drivers.
- 40 TTL digital inputs
- Utilising 40 of the unused DIO on the PXI-7851R reconfigurable IO FPGA card
- Simple FPGA code written to make availa-ble the status of the TTL inputs
- Windows software to read DIO status from the FPGA
- The end user customisation of the control labels on the GUI, DAQ device, port & channel by editing a simple ASCII file
- 32 high voltage (20V) pulsed transmit receive pairs
- PXI-6514 digital input output card
- Telemetry is a switch, pulses are sent and read using input output pairs using stand-ard DAQmx
- User customisation of the control labels on the GUI, DAQ device, ports & channels plus the pulse width by editing a simple ASCII file.
- 32 high voltage (20V) pulsed current sensed
- PXI-6512 digital output card & PXI-7851R reconfigurable mixed IO (FPGA) card (Analogue Inputs)
- Simple FPGA code to read in the ADC val-ues and make available to Windows code
- Telemetry is an Open circuit or short to ground type read by sending a short pulse and measuring the current via the voltage drop across a shunt resistor
- Custom built relay multiplexer to switch 32 channels across 8 available ADCs
- Windows code to initiate pulse, measure voltage & evaluate telemetry
- 80 analogue channels
- PXI-6225 80 analogue inputs & 24 digital input outputs
- Custom built relay multiplexer PCB with relay control via the DIO doubling analogue lines
- Providing Thermistor temperature and volt-age telemetry
Custom developed software interface developed in National Instruments LabVIEW graphical programming language, using a modular industry recognised architecture consisting of asynchronous processes for each interface type with overall inter process messaging handled from the main graphical user interface. This approach provides flexibility to adapt the individual software packages as the project progressed without compromising the other code modules. To provide the strict timing requirements for the LSSB communications link the actual signal write/read functionality was developed and compiled for deployment to a NI PXI FPGA card. The software provides the control required to power and configure the satellite payload along with readback and visualisation of the current status by interpreting the telemetry read on the various interfaces.